Communications system

ABSTRACT

An ATM communications system incorporates both broadband and narrowband services. A plurality of channels are adapted into groups, each group comprising a virtual circuit for transmission purposes. Each group is subsequently readapted back to individual channels. Any channel can be connected with any virtual circuit and each group of channels comprising a virtual circuit maintains time slot integrity throughout the adaptation and transmission process.

This invention relates to digital communications systems and inparticular to systems embodying asynchronous transfer mode (ATM)technology.

The asynchronous transfer mode (ATM) technology is a flexible form oftransmission which allows any type of service traffic, voice, video ordata, to be multiplexed together on to a common means of transmission.In order for this to be realised, the service traffic must first beadapted typically into 53 byte cells comprising 5 byte headers and 48byte payloads such that the original traffic can be reconstituted at thefar end of an ATM network. This form of adaptation is performed in theATM adaptation layer (AAL). Five types of adaptation layer have beendefined, this invention relates to adaptation layer 1 which is used toadapt constant bit rate traffic to the ATM standard.

A general description of a host interface for an ATM network is given inspecification number WO-A-9222034 which describes a method oftransmitting traffic carried in channels. A discussion of a hardwareimplementation of AAL and ATM protocol layers is given by G Marino etal. in Proceedings of Interworking '92, Amsterdam, 18 to 20 November1992, pages 166 to 178. The prototyping of an ATM adaptation layer in amultimedia terminal is discussed by G Armitage et al. in InternationalJournal of Digital and Analog Communication Systems, Vol. 6 No. 1,January 1993, pages 3 to 14.

An ATM exchange may support POTS or ISDN services as well as B-ISDNservices. The H320 Video conference standard is a typical user of ann×64 Kb/s service, this may well be embedded within a B-ISDN workstationand can also be supported by the N-ISDN. In an ATM exchange with 2 Mb/strunk circuits with independent calls on each 64 kb/s channel it isdesirable that traffic once adapted to ATM should remain in ATM up tothe destination narrowband port. It is further desirable that a physicaltrunk at e.g. 155 Mb/s should be able to carry logical routes to morethan one destination as 155 Mb/s is generally too large a capacity fortrunking within a narrowband service network. If the logical routes areof n×64 kb/s where n≧6 then the cell assembly delay is reduced to thepoint that echo cancellation is no longer necessary. The cell assemblydelay of a single 64 kb/s circuit is 6 msec which requires echocancellation for interworking with the existing narrowband network.

The object of the invention is to provide a flexible means to implementthe network requirements outlined above.

According to one aspect of the present invention there is provided anasynchronous transfer mode (ATM) communications system supporting bothbroadband and narrowband services carried in respective channels, thesystem including means for adapting a plurality of channels into groups,each said group comprising a virtual channel for transmission purposes,ingress and egress frame memories, means for staticising a synchronoustransport mode (STM) stream into the egress frame memory, means fordistributing the content of the ingress frame memory as an STM stream,and means for readapting each said group back to individual channels,wherein the adaptation and readaptation processes are controlled by achain structure, each link in the chain comprising two bidirectionalpointers and an address in the egress or ingress frame memory, therebeing one link per channel in each of the egress or ingress chains,wherein a said chain is assembled for each active ATM virtual circuit,and wherein the system is such that any individual channel can beassociated with any virtual channel, and that any said group of channelsmaintains time slot integrity throughout the adaptation and transmissionprocess

According to another aspect of the invention there is provided a methodof transmitting traffic carried in channels in an asynchronous transfermode (ATM) communications system supporting both broadband andnarrowband services carried in respective channels, the method includingfor adapting a plurality of channels into groups, each said groupcomprising a virtual channel for transmission purposes, ingress andegress frame memories, staticising a synchronous transport mode (STM)stream into the egress frame memory, distributing the content of theingress frame memory as an STM stream, and readapting each said groupback to individual channels such that any individual channel can beassociated with any virtual channel, and that any said group of channelsmaintains time slot integrity throughout the adaptation and transmissionprocess, wherein the adaptation and readaptation processes arecontrolled by a chain structure, each link in the chain comprising twobidirectional pointers and an address in the egress or ingress framememory, there being one link per channel in each of the egress oringress chains, and wherein a said chain is assembled for each activeATM virtual circuit.

Embodiments of the invention will now be described with reference to theaccompanying drawings in which:

FIG. 1 illustrates the function of the ATM adaptation layer 1 (AASL1);

FIG. 2 shows the ATM cell construction;

FIG. 3 illustrates the use of the ATM adaptation layer 1 for standarddata transfer;

FIG. 4 illustrates the interworking of N-ISDN with B-ISDN using theAAL1;

FIG. 5 shows the use of ATM switches for narrowband trunking;

FIG. 6 shows in schematic form a flexible AAL1 mechanism according toone embodiment of the invention;

FIG. 7 is a functional block diagram of the flexible AAL1 mechanism ofFIG. 6;

FIG. 8 shows an alternative flexible AAL1 mechanism;

FIG. 9 is a functional block diagram of the mechanism of FIG. 8;

FIG. 10 illustrates the time slot integrity of the arrangement of FIG.8; and

FIG. 11 illustrates the time slot interchange protocol of thearrangement of FIG. 8.

FIGS. 1 to 5 refer to the specification or protocol of the ATMadaptation layer 1 (AAL1) and are included here to facilitate theunderstanding of the invention. The generic functions performed by theAAL1 are illustrated in FIG. 1. The basic purpose of AAL1 is to segmenta synchronous transmission mode (STM) signal into ATM cells which can betransported across an ATM network and reassembled into an exact replicaof the STM stream at the far end. In order to achieve this, the STMstream is divided into 46 or 47 byte protocol data units (PDU) andassembled together with a segmentation and assembly (SAR)-PDU header andan optional pointer into the 48 byte payload of an ATM cell. This cellis then launched across an ATM network and is processed by an AAL1receiver processor to recreate the STM stream. The ATM network incursdelay in transfer of the cells and this delay may be subject tovariation depending on the traffic situation, cells are thereforebuffered at the receive processor so that any delay variation can beeliminated.

The content of the SAR-PDU header is illustrated in FIG. 2, the basicfunction is to provide a sequence count in order to detect lost ormisdirected cells and an error check on the sequence count in order toensure the integrity of the process of this detection. AAL1 supports twotypes of adaptation: asynchronous which is used for systems with a clockwhich is independent of the ATM network, e.g. the 3 Mb/s G703 system andsynchronous e.g. n×64 kb/s where the clock is synchronised to the ATMsystem clock. This invention is related to the synchronous form oftransfer. In order to identify the individual channels it is necessaryto indicate the starting byte of a frame of n×64 kb/s data. This isachieved by the AAL1 structured data transfer mechanism as illustratedin FIG. 3. The CSI bit within the SAR-PDU header is used to indicatewhether a pointer byte is contained within the payload, if a pointerbyte is present then this indicates the start of an n×64 kb/s frameanywhere within the combined 93 bytes of two PDU's.

FIG. 4 illustrates the manner in which an ATM exchange can support POTSor ISDN services as well as B-ISDN services. In FIG. 4, the arrowsrepresent AAL1 switched channels carrying multiple cells. POTS andnarrow band service interfaces are adapted by the ATM switches to carryindividual calls.

FIG. 5 illustrates the manner in which traffic, once adapted to ATM,services in the ATM format up to the destination narrowband port. TheAAL1 switched channel connection is carried between the two AAL1switches at the adaptation points. The signalling for the purpose ofnarrow band calls may be via narrow band ISUP at the end exchanges. eachcall request leads to an additional 64 kb/s channel being allocated onthe n×64 kb/s switched channels. Where additional switched channels arerequired, these are created by SVCs using the broadband ISUP signallingwithin the ATM network.

In a typical narrowband telecommunications system a common STM bus isavailable on the backplane of the equipment. This is used as theinterface between the equipment which adapts external interfaces such asanalogue or ISDN lines and the equipment which performs the intrinsicfunction such as switching. An equipment which adapts to an externalSTM1 system would typically have 2048 64 kb/s channels available on thebackplane to the adaptation function. The purpose of the presentinvention is to allow the adaptation of a number of 64 kb/s channels,say 2048, into a number of n×64 kb/s ATM virtual circuits and there-adaptation to 64 kb/s channels within the following constraints:-

Any 64 kb/s channel can be associated with any ATM virtual circuit

Any group of P 64 kb/s channels can be assembled together as part orwhole of an ATM virtual circuit and will maintain time slot sequenceintegrity throughout the adaptation and transmission processes.

For conformance to AAL1 standards n is restricted to values from 1 to30. For proprietary applications n can have any integer value up to thefull capacity of the system.

The number of ATM virtual circuits M can be any value up to the limit of1 64 Kb/s circuit per ATM VC i.e. 1≦M≦2048 for this example.

The principle of one embodiment of the mechanism is illustrated in FIG.6 and the functional block diagram of its implementation is illustratedin FIG. 7. In both diagrams a process is implied, but not shown, whichruns e.g. at 125 microsecond intervals and staticises the STM stream onthe backplane into an Egress frame memory and takes the contents of aningress frame memory and distributes this as an STM stream to thebackplane. The mechanism is controlled by a chain structure, each linkin the chain is embodied as a combination of two bi-directional pointersand an address in the egress or ingress frame memory, there is one linkfor each 64 kb/s channel in each of the egress and ingress chains.Chains are linked to headers and there is one header for each potentialn×64 Kb/s ATM virtual circuit, headers are embodied by the associationof a channel count for control purposes, a VC identity for cell assemblypurposes and a bidirectional pointer to the first link of the chain. Achain is assembled for each active ATM virtual circuit, it consists of anumber of links which use bi-directional pointers to point upwards tothe header or previous link and downwards to the next link. Each linkcontains the address in the frame memory of the required frame sample,these being taken in order to assemble an ATM cell one byte at a timefor the VC.

When a cell is filled it is dispatched. The reverse process unpacks acell one byte at a time and the memory address within the link is usedto store the unpacked byte in the Ingress frame memory.

An alternative embodiment is illustrated in FIGS. 8 to 11 of theaccompanying drawings. The principle of the mechanism is shown in FIG.8, and the functional block diagram of its implementation is shown inFIG. 9. The time slot integrity and the time slot interchange are shownin FIGS. 10 and 11 respectively. In FIGS. 8 to 11 a process is implied,but not shown, which cycles every 125 microseconds, and generates theaddress on the backplane, and supplies or accepts the relevant dataacross the backplane. The mechanism is controlled by the backplaneaddress, which is used either directly on indirectly to access theAddress to Connection Map Memory, which addresses at any one time, andonce only, each valid address in the entire address range of the framein each 125 microsecond cycle, which address may be each valid addressin an arbitrary order. Ordinarily there is a location in the memory foreach backplane address or each 64 Kb/s channel. As an optional, theingress and egress backplane cycles may be synchronised such that theaddress on each backplane is the same at any given instant, they mayshare the same address port of the map.

For the egress process the map contains either directly or indirectlyall the information necessary for assembling the frame byte data or 64Kb/s channel data into the payload of the corresponding ATM virtualcircuit, and the information for the construction of the header of thecells of the corresponding ATM Virtual Circuit, for which process thebackplane address is used to retrieve from the map the address in thecell payload memory of the ATM virtual circuit to which the 64 Kb/schannel corresponds, and retrieves any form of supplementary informationfrom the same map for the purposes of cell assembly or disassembly,which supplementary information may comprise for the purposes of examplethe VCI/VPI of the ATM circuit, and which may also comprise the overalllength of the cell payload for each payload of the same ATM VirtualCircuit, such length may optionally be different from any conventionallength of ATM cell payloads, and such length may be different from othersimultaneous ATM virtual circuits cell payloads, and which may alsooptionally comprise an offset in the ATM cell payload and which may alsocomprise all manner of information and attribution per 64 Kb/s channelbyte and per ATM Virtual Circuit, the cell address being used to derivethe next available byte position in the corresponding cell payload,which payload when filled to the conventional length or a lengthdetermined as earlier is scheduled for dispatch by a scheduling process,which scheduling process assembles the payloads with their ATM Headerand AAL1 SAR-PDU Header using the cell address and supplementaryinformation either directly or indirectly from the map, which assembledcells are launched into the ATM, whereafter a new cell payload is begunfor the corresponding ATM Virtual Circuit. For the egress process theFrame address changes for each byte of frame data, which frame addressis used to retrieve the cell address from the map, which map may haveassigned the same cell address to more than one 64 Kb/s channel in thesame frame an arbitrary number of times. This method is used to assemblecell payloads for n×64 Kb/s channels for arbitrary n and for anarbitrary m ATM Virtual Circuits per 125 microsecond cycle, which celladdress may also be used to signify an unassigned channel which data isnot used for cell assembly purposes. Those skilled in the art willappreciate that the aforementioned scheduling process may dispatchassembled ATM cells with equal priority to each ATM Virtual Circuit, ormay favour certain virtual circuits by means of a prearranged priority,which priority may be provided for by means of the supplementaryinformation of the map.

For the ingress process in the same or other receiving equipment, theATM Virtual Circuit is determined by a header analysing process thatrelates the virtual circuit to a cell address by direct or indirectmeans of the supplementary information of the aforementioned map or byother means, which relationship between virtual circuit and cell addressmay be identical to or independent of the egress process, which headeranalyser removes the ATM Header and the AAL1 SAR-PDU Header and storesthe cell payload in a memory at the cell address, which cell payloadmemory is accessed by an ingress VC map process that determines the nextavailable byte in a cell payload to be put on the backplane as the Framebyte data from the Frame byte address, which address is used directly orindirectly to retrieve the cell address from the aforementioned orequivalent map, which process is the reverse of the egress process,which process may also check and process any error in the indication inthe AAL1 of the boundary of an n×64 Kb/s channel and the Frame.

An Ingress/Egress VC map update process operates under instructions fromthe System Control, which process operates a Request/Grant mechanismwith the Ingress/Egress VC Map process to ensure that the map is notmodified at the same time as it is being accessed, which process couldupdate the entire map in a single 125 microsecond cycle either ahead orbehind the Ingress/Egress VC Map process. The modifications may takeeffect in the same or next Frame cycle without any interruption or delayin processing the frame or ATM data. This process may straightforwardlyand arbitrarily change n for any and all ATM Virtual Circuits bychanging the cell address and supplementary information in any locationin the map without affecting any other location or the service provided.

The aforementioned mechanism optionally provides the direct ability toreserve n×64 Kb/s channels on a Virtual Circuit of which n, ×≦n mayrepresent 64 Kb/s channels in use, and where x may vary in time whenchannels fall into disuse or more of the n channels are utilised. Thisvariation may be arranged not to affect any other channel in the sameVirtual Circuit by means of an offset in the supplementary informationof the aforementioned map. In the egress process the operation is asdescribed wherein the backplane address is used to retrieve from the mapthe address in the cell payload memory of the ATM virtual circuit towhich the 64 Kb/s channel corresponds, and the offset of the 64 Kb/schannel data in a sub-frame in the payload of the cell. The sub-frame isof length n in bytes, where n is not necessarily a factor of the payloadlength of the cell, which offset is less than n and greater than zero.The offset is different for each 64 Kb/s channel in the 125 microsecondframe which corresponds to the same ATM Virtual Circuit, and retrievesany form of aforementioned supplementary information from the same mapfor the purposes of cell assembly or disassembly. The cell address andthe offset are used to derive the next available byte position in thecorresponding cell payload. The offset enables the 64 Kb/s channel datato be assembled into the cell payload in an order that may differ fromthe time sequence order in an arbitrary manner, which payload whenfilled to the conventional length or a length determined as earlier isscheduled for dispatch by a scheduling process as described above.

For the ingress process, the mechanism is as described for theconventional operation, wherein the ATM Virtual Circuit is determined bya header analysing process that relates the virtual circuit to a celladdress. The header analyser removes the ATM Header and the AAL1 SAR-PDUHeader and stores the cell payload in a memory at the cell address. Thecell payload memory is accessed by an ingress VC map process thatdetermines the next available byte in a cell payload to be put on thebackplane as the Frame byte data from the Frame byte address, whichaddress is used directly or indirectly to retrieve the cell address andthe offset from the aforementioned or equivalent map. The cell addressand offset determine the next byte of the cell payload. The process,which is the reverse of the egress process, may also check and processany error in the indication in the AAL1 of the boundary of an n×64 Kb/schannel and the Frame.

Those skilled in the art will appreciate that the offsets in the ingressand egress map may differ, and the Virtual Circuits of a time slot or 64Kb/s channel may differ, to the extent that the aforementioned mechanismdirectly provides the ability to perform time slot interchange withoutany loss of generality between ingress and egress backplanes.

We claim:
 1. An asynchronous transfer mode (ATM) communications systemsupporting both broadband and narrowband services carried in respectivechannels, the system including means for adapting a plurality ofchannels into groups, each said group comprising a virtual channel fortransmission purposes, ingress and egress frame memories, means forstoring a synchronous transport mode (STM) stream into the egress framememory, means for distributing the content of the ingress frame memoryas an STM stream, and means for readapting each said group of channelsback to individual channels, wherein the adaptation and re-adaptationprocesses are controlled by a chain structure of control data, therebeing one link per channel in each of the egress or ingress chains,wherein a said chain is assembled for each active ATM virtual circuit,each link in the chain comprising two bidirectional pointers to theprevious and successive links respectively and incorporating arespective address in the egress or ingress frame memory for effectingsaid storing and redistribution in an ordered manner whereby any saidgroup of channels maintains time slot integrity throughout theadaptation and transmission process.
 2. A communications system asclaimed in claim 1, and including means for mapping into each assembledcell or payload the information necessary for the frame byte data orchannel data and the information from the construction of the header ofthe cells of the corresponding ATM virtual circuit.
 3. A communicationssystem as claimed in claim 2, wherein the readaptation process includesmapping of a said virtual circuit to a corresponding cell address.
 4. Amethod of transmitting traffic carried in channels in an asynchronoustransfer mode (ATM) communications system supporting both broadband andnarrowband services carried in respective channels, the method includingfor adapting a plurality of channels into groups, each said groupcomprising a virtual channel for transmission purposes, ingress andegress frame memories, storing a synchronous transport mode (STM) streaminto the egress frame memory, distributing the content of the ingressframe memory as an STM stream, and readapting each said group ofchannels back to individual channels such that any individual channelcan be associated with any virtual channel, wherein the adaptation andre-adaptation processes are controlled by a chain structure of controldata, there being one link per channel in each of the egress or ingresschains, wherein a said chain is assembled for each active ATM virtualcircuit, each link in the chain comprising two bidirectional pointers tothe previous and successive links respectively and incorporating arespective address in the egress or ingress frame memory for effectingsaid storing and redistribution in an ordered manner whereby any saidgroup of channels maintains time slot integrity throughout theadaptation and transmission process.
 5. A method as claimed in claim 4,and including mapping into each assembled cell or payload theinformation necessary for the frame byte data or channel data and theinformation from the construction of the header of the cells of thecorresponding ATM virtual circuit.
 6. A method as claimed in claim 5,wherein the readaptation process includes mapping of a said virtualcircuit to a corresponding cell address.